1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a semiconductor memory device including a circuit receiving an input signal and decoding the input signal.
2. Description of the Background Art
FIG. 23 is a block diagram showing a configuration of a conventional synchronous static random access memory (hereinafter referred to as a synchronous SRAM).
The synchronous SRAM includes a memory cell array 7, a row address buffer 202, a latch circuit 211, a row address decoder 203, a column address buffer 205, a latch circuit 212, a column address decoder 206, a multiplexer 8, a read/write circuit 9, a data input/output buffer/latch circuit 10, and a read/write control circuit 16.
In memory cell array 7, memory cells storing information are arranged in a matrix manner. Row address buffer 202 and latch circuit 211 receive an externally applied row address signal RADD, and amplifies, and inverts and amplifies row address signal RADD for holding. Row address decoder 203 decodes the row address signal applied from latch circuit 211.
Column address buffer 205 and latch circuit 212 amplifies, and inverts and amplifies an externally applied column address signal CADD for holding. Column address decoder 206 decodes the column address signal applied from latch circuit 212.
In response to an output signal from column address decoder 206, multiplexer 8 provides write data applied from read/write circuit 9 to memory cell array 7, and provides read data from memory cell array 7 to read/write circuit 9.
Read/write circuit 9 includes a sense amplifier for reading which senses and amplifies a read voltage of a small amplitude, and a write buffer for writing. Data input/output buffer/latch circuit 210 includes an output data buffer for amplifying and holding an output from the sense amplifier of read/write circuit 9, and an input data buffer for amplifying and holding an externally applied signal indicating write data WD.
Data input/output buffer/latch circuit 210 amplifies a signal, applied from read/write circuit 9, indicating read data and provides the amplified signal to the outside world, and amplifies an externally applied signal indicating write data and provides the amplified signal to read/write circuit 9. Read/write control circuit 16 receives a chip enable signal CE and a write enable signal WE, and controls read/write circuit 9 and data input/output buffer/latch circuit 210 in response to these signals.
FIG. 24 is a block diagram showing a detailed configuration of a peripheral portion of memory cell array 7 of the synchronous SRAM shown in FIG. 23. In this figure, for simplicity of description, the case where memory cells of memory cell array 7 are arranged in two rows and two columns is described.
Referring to FIG. 24, in memory cell array 7, memory cells 224a, 224b, 224c, 224d are arranged at respective crossing points of word lines 222 and 223 connected to row address decoder 203 and bit line pairs 220a, 220b, and 221a, 221b.
Bit line loads 225a, 225b, 226a, 226b are connected between a power supply node 90 receiving a power supply potential and bit lines 220a, 220b, 221a, 221b.
An I/O line pair 229a, 229b is connected to read/write circuit 9. Transfer gates 227a, 228a are connected between bit lines 220a and 221a, and I/O line 229a, respectively. Transfer gates 227a, 228a each receive an output signal from column address decoder 206 at its gate.
Transfer gates 227b, 228b are connected between bit lines 220b and 221b, and I/O line 229b, respectively. Transfer gates 227b and 228b each receive an output signal from column address decoder 206 at its gate.
Read/write circuit 9 amplifies a potential difference between I/O lines 229a, 229b, and provides the amplified signal to data input/output buffer/latch circuit 210. Data input/output buffer/latch circuit 210 amplifies an output signal from read/write circuit 9 and provides the amplified signal as read data RD.
When memory cell 224a is selected, for example, the following operation is carried out. In response to a row address signal applied to row address decoder 203, word line 222 to which memory cell 224a is connected is brought to a selected level (for example, an H level), and another word line 223 is brought to a non-selected level (for example, an L level).
In response to a column address signal applied to column address decoder 206, transfer gates 227a, 227b corresponding to bit line pair 220a, 220b to which memory cell 224a is connected are rendered conductive.
As a result, bit line pair 220a, 220b is connected to I/O line pair 229a, 229b, and another bit line pair 221a, 221b is disconnected from I/O line pair 229a, 229b.
In reading data, write enable signal WE applied to read/write circuit 9 through read/write control circuit 16 is brought to the L level, and I/O line pair 229a, 229b is disconnected from a data input terminal 12. In this case, chip enable signal CE applied to read/write circuit 9 through read/write control circuit 16 is brought to the H level, and the sense amplifier of read/write circuit 9 is brought to an operating state.
Word line 222 or 223 is selected by row address decoder 203, and all the memory cells connected to the selected word line are activated. At the same time, bit line pair 220a, 220b or 221a, 221b is selected by column address decoder 206. As a result, data is read out to I/O line pair 229a, 229b from a memory cell selected by the word line and the bit line pair.
By the data reading, a potential difference generated between I/O lines 229a, 229b is amplified by the sense amplifier of read/write circuit 9, and the amplified signal is applied to data input/output buffer/latch circuit 210.
FIG. 25 is a circuit diagram showing one example of a configuration of latch circuit 211.
Referring to FIG. 25, the latch circuit includes an NMOS transistor 231 and inverters 233, 235 and 237. In this latch circuit, an input terminal 230 receives an output signal from row address buffer 202, and NMOS transistor 231 receives a synchronous signal CLK. An output signal is provided from an output terminal 236 to row address decoder 203 of FIG. 23.
When synchronous signal CLK is at the H level, a signal applied through input terminal 230 is applied to output terminal 236 through NMOS transistor 231, inverters 233 and 235, and latched by inverters 233 and 237. On the other hand, when synchronous signal CLK is at the L level, the signal latched by inverters 233 and 237 is applied to output terminal 236 through inverter 235.
Another example of latch circuit 211 of FIG. 23 will now be described. FIG. 26 is a circuit diagram showing another example of the configuration of latch circuit 211. The latch circuit of FIG. 26 includes two stages of latch circuits shown in FIG. 25 connected in series.
Referring to FIG. 26, the latch circuit includes NMOS transistors 241 and 248, and inverters 243, 245, 247, 250, 252 and 254.
An input terminal 240 receives an output signal from row address buffer 202. NMOS transistor 241 receives synchronous signal CLK at its gate. NMOS transistor 248 receives an inverted synchronous signal /CLK ("/" indicates an inverted signal hereinafter) which is an inverted signal of synchronous signal CLK at its gate. An output terminal 253 provides an output signal to row address decoder 203 of FIG. 23.
When synchronous signal CLK is at the H level, NMOS transistor 241 is rendered conductive. Therefore, a signal applied through input terminal 240 is transmitted to a node 246 between inverter 245 and NMOS transistor 248 through NMOS transistor 241, and inverters 243 and 245. Simultaneously, the signal is latched by inverters 243 and 247.
When inverted synchronous signal /CLK attains the H level, NMOS transistor 248 is rendered conductive. Therefore, the signal transmitted to node 246 is transmitted to an output terminal 253 through NMOS transistor 248, and inverters 250 and 252. Simultaneously, the signal is latched by inverters 250 and 254.
More specifically, when synchronous signal CLK is at the H level, a signal is latched by inverters 243 and 247. When inverted synchronous signal /CLK attains the H level, the latched signal is latched by inverters 250 and 254, and transmitted to output terminal 253.
Description will now be given of timings of address selection operation in the SRAM of FIG. 23 with reference to a timing chart shown in FIG. 27.
In FIG. 27, shown are synchronous signal CLK, a predecode signal PDO provided from row address buffer 202, a latch output signal LO provided from latch circuit 211, a subdecoder output signal SDO in row address decoder 203, and a word line select signal WL. Subdecoder output signal SDO is an output signal from a subdecoder included in row address decoder 203.
Referring to FIG. 27, when a word line is selected, row address signal RADD corresponding to a word line to be selected is applied to row address buffer 202. In row address buffer 202, applied row address signal RADD is amplified, inverted and amplified, and predecoded. Applied row address signal RADD is converted into an internal signal, and provided as predecode signal PDO which is an internal signal. Predecode signal PDO is latched in response to synchronous signal CLK in latch circuit 211, and transmitted to row address decoder 203.
In row address decoder 203, in response to latch output signal LO provided from latch circuit 211, subdecoder output signal SDO changes, and, in response to this, line select signal WL changes.
In row address decoder 203, timings of selection and non-selection of a word line are so set that both have approximately the same delay time from change of row address signal RADD. More specifically, selection and non-selection of a word line are carried out at the same timing. A particular word line is brought to a selected level in response to word line select signal WL in row address decoder 203, and the other word lines are brought to a non-selected level.
Similarly, a bit line pair is selected. In this case, a column address signal corresponding to a bit line pair to be selected is applied to column address buffer 205.
In response to application of the column address signal, only a pair of transfer gates connected to the bit line pair to be selected is rendered conductive. Only the selected bit line pair is connected to I/O line pair 229a, 229b, and the other bit line pairs are disconnected from the I/O line pair.
In selection of a bit line pair, similar to the case of selection of a word line, timings of selection and non-selection are so set that both have approximately the same delay time from change of column address signal CADD.
As described above, in the conventional synchronous SRAM, in order to synchronize operation with synchronous signal CLK, latch circuit 211 was provided between row address buffer 202 and row address decoder 203, and latch circuit 212 was provided between column address buffer 205 and column address decoder 206.
Therefore, an address signal is strobed and latched only at a timing where synchronous signal CLK is in an active state, and the latched address signal is transmitted to an address decoder. Therefore, any word line and bit line pair are always selected.
Row address decoder 203 and column address decoder 206 were the same in timings of selection and non-selection of a word line or a bit line pair.
In the conventional synchronous SRAM, however, any word line or bit line pair is always selected. If the timing of selection and the timing of non-selection are not set equal, multiple selection occurs. Therefore, in order to increase the operation speed, both selection operation and non-selection operation must be carried out at a high speed, resulting in difficulty of increase of the operation speed. This is because, for example, it is necessary to increase in size both a transistor for carrying out selection operation and a transistor for carrying out non-selection operation.